View MC14489_8915650.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC14489 motorola 1

cmos the m c1448 9 i s a f lexibl e l ightemittingdiod e d rive r w hich d irectly interfaces to individual lamps, 7segment displays, or various combinations of both. leds wired with common cathodes are driven in a multiplexedby5 fashion. communication with an mcu/mpu is established through a synchro - nous serial port. the MC14489 features data retention plus decode and scan circuitry, thus relieving processor overhead. a single, currentsetting resistor is the only ancillary component required. a single device can drive any one of the following: a 5digit display plus decimals, a 41/2digit display plus decimals and sign, or 25 lamps. a special technique allows driving 5 1/2 digits; see figure 16. a configuration register allows t h e d riv e c apabilit y t o b e p artitioned o f f t o s ui t m an y a dditional applications. the onchip decoder outputs 7segmentformat numerals 0 to 9, hexadecimal characters a to f, plus 15 letters and symbols. the MC14489 is compatible with the motorola spi and national micro - wire ? serial data ports. the chip' s patented bitgrabber ? registers augment the serial interface by allowing random access without steering or address bits. a 2 4bi t t ransfe r u pdate s t he d ispla y r egister . c hangin g t h e c onfiguration register requires an 8bit transfer. ? operating voltage range of drive circuitry: 4.5 to 6 v ? operating junction temperature range: 40 to 130 c ? current sources controlled by single resistor provide anode drive ? lowresistance fet switches provide direct common cathode interface ? lowpower mode (extinguishes the leds) and brightness controlled via serial port ? special circuitry minimizes emi when display is driven and eliminates emi in lowpower mode ? poweron reset (por) blanks the display on powerup, independent of supply ramp up time ? may be used with doubleheterojunction leds for optimum efficiency ? chip complexity: 4300 elements (fets, resistors, capacitors, etc.) ? see application note an431, temperature measurement and display using the mc68hc05b4 and the MC14489 and engineering bulletin eb153, driving a sevensegment display with the n euron ? c hip bitgrabber is a trademark of motorola inc. microwire is a trademark of national semiconductor corp. order this document by MC14489/d semiconductor technical data pin assignment p suffix plastic dip case 738 dw suffix sog package case 751d ordering information MC14489p plastic dip MC14489dw sog package b d v dd e f enable bank 1 rx a c 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 bank 4 bank 5 data out h g clock data in bank 2 v ss bank 3 20 1 20 1 ? motorola, inc. 1995 rev 3 10/95
MC14489 motorola 2 block diagram 1 bitgrabber configuration register 8 bits rx data out 8 2 20 12 bitgrabber display register 24 bits nibble mux and decoder rom anode drivers (current sources) bank switches (fets) 19 4 5 6 7 a b data in c d e f g h 241/2stage shift register 11 10 7 4 4 4 4 4 4 4 4 4 4 4 4 18 por 9 13 15 16 17 5 5 clock enable oscillator and control logic bank 1 bank 2 bank 3 bank 4 bank 5 pin 3 = v dd pin 14 = v ss h dim/bright blank a to g d c maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 0.5 to + 6.0 v v in dc input voltage 0.5 to v dd + 0.5 v v out dc output voltage 0.5 to v dd + 0.5 v i in dc input current e per pin (includes pin 8) 15 ma i out dc output current e pins 1, 2, 4 7, 19, 20 sourcing sinking 40 10 ma pins 9, 13, 15, 16, 17 sinking 320 pin 18 15 i dd , i ss dc supply current, v dd and v ss pins 350 ma t j chip junction temperature 40 to + 130 c r q ja device thermal resistance, junctiontoambient (see thermal considerations section) plastic dip sog package 90 100 c/w t stg storage temperature 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. this device contains protection circuitry to guard against damage due to high static volt - ages or electric fields. however , precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an ap - propriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
MC14489 motorola 3 electrical characteristics (voltages referenced to v ss , t j = 40 to 130 c* unless otherwise indicated) symbol parameter test condition v dd v guaranteed limit unit v dd power supply voltage range of led drive circuitry e 4.5 to 6.0 v v dd (stby) minimum standby voltage bits retained in display and configuration registers, data port fully functional e 3.0 v v il maximum lowlevel input voltage (data in, clock, enable ) 3.0 6.0 0.9 1.8 v v ih minimum highlevel input voltage (data in, clock, enable ) 3.0 6.0 2.1 4.2 v v hys minimum hysteresis voltage (data in, clock, enable ) 3.0 6.0 0.2 0.4 v v ol maximum lowlevel output voltage (data out) i out = 20 m a 3.0 6.0 0.1 0.1 v i out = 1.3 ma 4.5 0.4 v oh minimum highlevel output voltage (data out) i out = 20 m a 3.0 6.0 2.9 5.9 v i out = 800 m a 4.5 4.1 i in maximum input leakage current (data in, clock, enable ) v in = v dd or v ss 6.0 2.0 m a (data in, clock, enable ) v in = v dd or v ss , t j = 25 c only 6.0 0.1 i ol minimum sinking current (a, b, c, d, e, f, g, h) v out = 1.0 v 4.5 0.2 ma i oh peak sourcing current e see figure 9 for currents up to 35 ma (a, b, c, d, e, f, g, h) rx = 2.0 k w , v out = 3.0 v, dimmer bit = high 5.0 13 to 17.5 ma rx = 2.0 k w , v out = 3.0 v, dimmer bit = low 5.0 6 to 9 i oz maximum output leakage current (bank 1, bank 2, bank 3, bank 4, bank 5) v out = v dd (fet leakage) 6.0 50 m a (bank 1, bank 2, bank 3, bank 4, bank 5) v out = v dd (fet leakage), t j = 25 c only 6.0 1 v out = v ss (protection diode leakage) 6.0 1 r on maximum on resistance (bank 1, bank 2, bank 3, bank 4, bank 5) i out = 0 to 200 ma 5.0 10 w i dd , i ss maximum quiescent supply current device in lowpower mode, v in = v ss or v dd , rx in place, outputs open 6.0 100 m a same as above, t j = 25 c 6.0 20 i ss maximum rms operating supply current (the v ss leg does not contain the rx current component. see pin descriptions.) device not in lowpower mode, v in = v ss or v dd , outputs open 6.0 1.5 ma * see thermal considerations section.
MC14489 motorola 4 ac electrical characteristics (t j = 40 to 130 c*, c l = 50 pf, input t r = t f = 10 ns) symbol parameter v dd v guaranteed limit unit f clk serial data clock frequency, single device or cascaded devices note: refer to clock t w below (figure 1) 3.0 4.5 6.0 dc to 3.0 dc to 4.0 dc to 4.0 mhz t plh , t phl maximum propagation delay, clock to data out (figures 1 and 5) 3.0 4.5 6.0 140 80 80 ns t tlh , t thl maximum output transistion time, data out (figures 1 and 5) 3.0 4.5 6.0 70 50 50 ns f r refresh rate e bank 1 through bank 5 (figures 2 and 6) 3.0 4.5 6.0 na 700 to 1900 700 to 1900 hz c in maximum input capacitance e data in, clock, enable e 10 pf * see thermal considerations section. timing requirements (t j = 40 to 130 c*, input t r = t f = 10 ns unless otherwise indicated ) symbol parameter v dd v guaranteed limit unit t su , t h minimum setup and hold times, data in versus clock (figure 3) 3.0 4.5 6.0 50 40 40 ns t su , t h , t rec minimum setup, hold, ** and recovery t imes, enable versus clock (figure 4) 3.0 4.5 6.0 150 100 100 ns t w(l) minimum activelow pulse width, enable (figure 4) 3.0 4.5 6.0 4.5 3.4 3.4 m s t w(h) minimum inactivehigh pulse width, enable (figure 4) 3.0 4.5 6.0 300 150 150 ns t w minimum pulse width, clock (figure 1) 3.0 4.5 6.0 167 125 125 ns t r , t f maximum input rise and fall times e data in, clock, enable (figure 1) 3.0 4.5 6.0 1 1 1 ms * see thermal considerations section. ** for a highspeed 8clock access, t h for enable is determined as follows: v dd = 3 to 4.5 v, f clk > 1.78 mhz: t h = 4350 (7500/f clk ) v dd = 4.5 to 6 v, f clk > 2.34 mhz: t h = 3300 (7500/f clk ) where t h is in ns and f clk is in mhz. notes: 1. this restriction does not apply for f clk rates less than those listed above. for aslowo f clk rates, use the t h limits in the above table. 2. this restriction does not apply for an access involving more than 8 clocks. for > 8 clocks, use the t h limits in the above table.
MC14489 motorola 5 figure 1. figure 2. 10% v dd 1/f clk data out clock 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r bank output 50% 1/f r v ss figure 3. figure 4. d ata in clock 50% valid 50% t su t h v dd v dd clock enable 50% t su t h first clock last clock t rec 50% v dd v dd t w (h) t w (l) v ss v ss v ss v ss figure 5. figure 6. test point device under test c l * * includes all probe and fixture capacitance. test point device under test c l * * includes all probe and fixture capacitance. v dd 56 w
MC14489 motorola 6 pin descriptions digital interface data in (pin 12) serial data input. the bit stream begins with the msb and is shifted in on the lowtohigh transition of clock. when the device is not cascaded, the bit pattern is either 1 byte (8 bits) long to change the configuration register or 3 bytes (24 bits) long to update the display register . for two chips cascaded, the pattern is either 4 or 6 bytes, respectively . the display does not change during shifting (until enable makes a low tohigh transition) which allows slow serial data rates, if de - sired. the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the two registers. ran - dom access of either register is provided. that is, the regis- ters may be accessed in any sequence. data is retained in the registers over a supply range of 3 to 6 v . the format is shown in figures 7 and 8. information on the segment de - coder is given in table 1. data in typically switches near 50% of v dd and has a schmitttriggered i npu t b uffer . t hes e f eature s c ombin e t o maximize noise immunity for use in harsh environments and bus a pplications . t hi s i npu t c a n b e d irectl y i nterface d t o cmos devices with outputs guaranteed to switch near rail torail. when interfacing to nmos or ttl devices, either a level shifter (mc14504b, mc74hct04a) or pullup resistor of 1 k w to 10 k w must be used. parameters to be considered when sizing the resistor are the worstcase i ol of the driving device, maximum tolerable power consumption, and maxi - mum data rate. clock (pin 11) serial data clock input. lowtohigh transitions on clock shift bits available at data in, while hightolow transitions shift bits from data out. the chip's 241/2stage shift regis- ter is static, allowing clock rates down to dc in a continuous or intermittent mode. the clock input does not need to be synchronous with the onchip clock oscillator which drives the multiplexing circuit. eight clock cycles are required to access the configuration register, while 24 are needed for the display register when the MC14489 is not cascaded. see figures 7 and 10. as shown in figure 1 1, two devices may be cascaded. in this case, 32 clock cycles access the configuration register and 48 access the display register, as depicted in figure 8. cascading of 3, 4, and 5 devices is shown in figures 12, 13, and 14, respectively. clock t ypicall y s witche s n ea r 5 0 % o f v dd a n d h a s a schmitttriggered input buffer. slow clock rise and fall times are tolerated. see the last paragraph of data in for more in- formation. note to guarantee proper operation of the poweron reset (por) circuit, the clock pin must not be floated or toggled during powerup. that is, the clock p i n m us t b e stable u nti l t h e v dd p in reaches at least 3 v. if control of the clock pin during powerup is not practical, then the MC14489 must be reset via bit c0 in the c register . to accomplish this, c0 is re - set low, then set high. enable (pin 10) activelow enable input. this pin allows the MC14489 to be used on a serial bus, sharing data in and clock with other peripherals. when enable is in an inactive high state, data out is forced to a known (low) state, shifting is inhibited, and the port is held in the initialized state. t o transfer data to the device, enable (which initially must be inactive high) is taken low, a s eria l t ransfe r i s m ad e v i a d at a i n a n d c lock , a nd enable is taken high. the lowtohigh transition on enable transfers data to either the configuration or display register , depending on the data stream length. every rising edge on enable initiates a blanking interval while data is loaded. thus, continually loading the device with the same data may cause the leds on some banks to appear dimmer than others. note transitions o n e nable m us t n o t b e a ttempted while clock is high. this puts the device out of synchronization with the microcontroller . resyn- chronization o ccur s w he n e nable i s h ig h a nd clock is low. this i npu t i s a ls o s chmitttriggered a n d s witche s n ear 50% of v dd , thereby minimizing the chance of loading erro- neous data in the registers. see the last paragraph of data in for more information. data out (pin 18) serial data output. data is transferred out of the shift reg- ister through data out on the hightolow transition of clock. this output is a no connect, unless used in one of the man - ners discussed below. when cascading MC14489' s, data out feeds data in of the next device per figures 11, 12, 13, and 14. data out could be fed back to an mcu/mpu to perform a wraparound test of serial data. this could be part of a sys - tem check conducted at powerup to test the integrity of the system's processor, pc board traces, solder joints, etc. the pin could be monitored at an inline q.a. test during board manufacturing. finally, data out facilitates troubleshooting a system. display interface rx (pin 8) external currentsetting resistor. a resistor tied between this pin and ground (v ss ) determines the peak segment drive current delivered at pins a through h. pin 8' s resistor ties into a current mirror with an approximate current gain of 10 when bit d23 = high (brighten). with d23 = low , the peak current is reduced about 50%. v alues for rx range from 700 w to infin- ity. when rx = (open circuit), the display is extinguished. for proper current control, resistors having 1% tolerance should be used. see figure 9. caution small rx values may cause the chip to overheat if precautions are not observed. see thermal considerations.
MC14489 motorola 7 a through h (pins 1, 2, 4 7, 19, 20) anodedriver current sources. these outputs are close - lymatched current sources which directly tie to the anodes of external discrete leds (lamps) or display segment leds. each output is capable of sourcing up to 35 ma. when used with lamps, outputs a, b, c, and d are used to independently control up to 20 lamps. output h is used to control u p t o 5 l amps d ependently . ( se e f igur e 1 7. ) f or lamps, the no decode mode is selected via the configuration register, forcing e, f, and g inactive (low). when used with segmented displays, outputs a through g drive segments a through g, respectively . output h is used to drive the decimals. if unused, h must be left open. refer to figure 10. bank 1 through bank 5 (pins 9, 13, 15, 16, 17) diodebank fet switches. these outputs are lowresis - tance switches to ground (v ss ) capable of handling currents of up to 320 ma each. these pins directly tie to the common cathodes of segmented displays or the cathodes of lamps (wired with cathodes common). the display is refreshed at a nominal 1 khz rate to achieve optimum brightness from the leds. a 20% duty cycle is uti - lized. special design techniques are used onchip to accommo- date the high currents with low emi (electromagnetic interfer - ence) and minimal spiking on the power lines. power supply v ss (pin 14) mostnegative supply potential. this pin is usually ground. resistor rx is externally tied to ground (v ss ). therefore, the chip' s v ss pin does not contain the rx current compo - nent. v dd (pin 13) mostpositive supply potential. to guarantee data integrity in the registers and to ensure the serial interface is functional, this voltage may range from 3 to 6 volts with respect to v ss . for example, within this volt- age range, the chip could be placed in and out of the low power mode. to adequately drive the leds, this voltage must be 4.5 to 6 volts with respect to v ss . the v dd pin contains the rx current component plus the chip's current drain. in the lowpower mode, the current mir - ror and clock oscillator are turned of f, thus significantly re - ducing the v dd current, i dd .
MC14489 motorola 8 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? figure 7. timing diagrams for noncascaded devices ??? ??? ??? ??? ??? ??? ??? d22 ??? ??? ??? d21 ??? ??? ??? d20 ??? ??? ??? d19 ??? ??? ??? d18 ??? ??? ??? d17 ??? ??? ??? d16 ??? ??? ??? ??? d15 ??? ??? ??? d14 ??? ??? ??? ??? d13 ??? ??? ??? d12 ??? ??? ??? d11 ??? ??? ??? d10 ??? ??? ??? d9 ??? ??? ??? d8 ??? ??? ??? d7 ??? ??? ??? ??? d6 ??? ??? ??? d5 ??? ??? ??? ??? d4 ??? ??? ??? d3 ??? ??? ??? d2 ??? ??? ??? d1 ??? ??? ??? ??? ??? d0 ??? ??? ??? ??? ??? ??? d23 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 msb lsb l = dim leds, h = brighten leds the lsbs of each bank nibble are d0, d4, d8, d12, and d16. bank 5 note: the lowpower (standby) mode places the device c6 c5 c4 c3 c2 c1 c7 2 3 4 5 6 7 8 1 msb enable clock data in in a static state, thus eliminating emi and mux switching noise. therefore, during precision analog measurements, the lowpower mode could be invoked by a system' s mcu. also, the lowpower mode blanks the display , and could be used to flash the leds on and of f. c0 l = low power mode (blanks the displa y), forced low (l) by power on reset h = normal mode controls bank 1: controls bank 2: l = hex decode, h = depends on c6 controls bank 3: l = hex decode, h = depends on c6 controls bank 4: l = hex decode, h = depends on c7 controls bank 5: l = hex decode, h = depends on c7 see table 1 l = no decode, h = special decode (refer to c1, c2, and c3) l = no decode, h = special decode (refer to c4 and c5) l l l l h h h h l l h h l l h h l h l h l h l h = all h outputs inactive = activate h in bank 1 = activate h in bank 2 = activate h in bank 3 = activate h in bank 4 = activate h in bank 5 = activate h in both banks 1 and 2 = activate h in all banks nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble see table 1 enable clcok data in lsb (a) configuration register format (1 byte) (b) display register format (3 bytes) note: l = low v oltage level (logic 0), h = high v oltage level (logic 1) l = hex decode, h = depends on c6
MC14489 motorola 9 table 1. triplemode segment decoder function table lamp conditions bank nibble value 7segment display characters no decode (invoked via bits c1 to c7) hexadecimal binary msb lsb hex decode (invoked via bits c1 to c5) special decode (invoked via bits c1 to c7) d c b a $0 $1 $2 $3 l l l l l l l h l l h l l l h h on on on on $4 $5 $6 $7 l h l l l h l h l h h l l h h h on on on on on on on on $8 $9 $a $b h l l l h l l h h l h l h l h h on on on on on on on on $c $d $e $f h h l l h h l h h h h l h h h h on on on on on on on on on on on on notes: 1. in the no decode mode, outputs e, f, and g are unused and are all forced inactive (low). output h decoding is unaffected, i.e., unchanged from the other modes. the no decode mode is used for three purposes: a. individually controlling lamps. b. controlling a half digit with sign. c. controlling annunciators - examples: am, pm, uhf , kv, mm hg. 2. can be used as capital s. 3. can be used as capital b. 4. can be used as small g.
MC14489 motorola 10 (a) configuration registers c7 c6 c5 c4 c3 c2 c1 c0 1st byte shifted in 2nd byte 3rd byte 4th byte configuration register of device 2 in figure 11 configuration register of device 1 in figure 11 don't care don't care (b) display registers figure 8. bit stream formats for two devices cascaded d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1st byte shifted in 2nd byte 3rd byte 4th byte h bits and dimmer bit h bits and dimmer bit 5th byte bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble 6th byte display register of device 2 in figure 11 display register of device 1 in figure 11 note: enable (which initially must be inactive high) is kept activelow during the entire 4byte configuration transfer or 6byte display transfer. when enable is brought back high, either a 4 or 6byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer. figure 9. a through h nominal current per output versus rx 35 30 25 20 15 10 5 400 800 1.2 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k 1.6 k i oh, peak drive current (ma) 5 v supply bit d23 = high (brighten leds) with d23 = low, i oh is cut by ~ 50%. rx, external resistor ( w ) note: drive current tolerance is approximately 15%.
MC14489 motorola 11 applications information figure 10. noncascaded application example: 5 character common cathode led display with two intensities as controlled via serial port #5 #4 #3 #2 #1 8 8 8 8 8 8 d a b c e f g bank 5 bank 4 bank 3 bank 2 bank 1 d a b c e f g h optional cmos mcu/mpu + 5 v rx v dd v ss data out rx data in clock enable + 5 v MC14489 ? figure 11. cascading two devices optional cmos mcu/mpu data out clock enable MC14489 #1 data in data out clock enable MC14489 #2 data in a to h bank 1 to bank 5 a to h bank 1 to bank 5
MC14489 motorola 12 figure 12. bit stream formats for three devices cascaded a to h bank 1 to bank 5 bank 1 to bank 5 bank 1 to bank 5 a to h a to h MC14489 #1 MC14489 #2 MC14489 #3 data in clock data out data in clock data out data in clock data out optional c0 c1 c2 c3 c4 c5 c6 c7 cmos mcu/mpu don't care 1st byte shifted in 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th (last) byte don't care don't care don't care don't care configuration register of device #1 configuration register of device #2 configuration register of device #3 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 1st byte shifted in 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th (last) byte don't care (optional, see note) display register of device #3 display register of device #2 display register of device #1 h bits and dimmer bit h bits and dimmer bit h bits and dimmer bit bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble (a) cascading three devices (b) configuration registers (c) display registers enable enable enable note: when the leading adon't careo bytes are included, enable (which initially must be inactive high) is kept activelow during the entire 8byte configuration transfer or 10byte display transfer . when enable is brought back high, either an 8 or 10byte transfer occurs in the cascaded devices. alternatively , when updating the display registers, the one adon't careo byte can be eliminated as follows: (1) take enable active low , (2) transfer 6 bytes, (3) pulse enable inactive high, see t (h) spec, (4) transfer last 3 bytes, and (5) take enable inactive high. w
MC14489 motorola 13 figure 13. bit stream formats for four devices cascaded a to h bank 1 to bank 5 bank 1 to bank 5 bank 1 to bank 5 a to h a to h MC14489 #1 MC14489 #2 MC14489 #4 data in clock data out data in clock data out data in clock data out optional c0 c1 c2 c3 c4 c5 c6 c7 cmos mcu/mpu don't care 1st byte shifted in 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte don't care don't care don't care don't care configuration register of device #3 configuration register of device #4 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 1st byte shifted in 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 13th byte 14th (last) byte don't care (optional, see note) display register of device #4 display register of device #3 display register of device #1 bank 5 nibble bank 4 nibble bank 3 nibble bank 1 nibble bank 5 nibble bank 4 nibble bank 3 nibble bank 1 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble (a) cascading four devices (b) configuration registers bank 1 to bank 5 a to h MC14489 #3 data in clock data out 9th byte 10th byte 11th byte 12th (last) byte don't care don't care configuration register of device #1 configuration register of device #2 12th byte h bits and dimmer bit bank 5 nibble don't care (optional, see note) don't care enable enable enable enable h bits and dimmer bit bank 2 nibble h bits and dimmer bit bank 2 nibble (c) display registers note: when the leading adon't careo bytes are included, enable (which initially must be inactive high) is kept activelow during the entire 12byte configuration transfer or 14byte display transfer . when enable is brought back high, either a 12 or 14byte transfer occurs in the cascaded devices. alternatively , when updating the display registers, the two adon't careo bytes can be eliminated as follows: (1) take enable active low , (2) transfer 6 bytes, (3) pulse enable inactive high, see t (h) spec, (4) transfer last 6 bytes, and (5) take enable inactive high. w
MC14489 motorola 14 figure 14. bit stream formats for five devices cascaded a to h bank 1 to bank 5 bank 1 to bank 5 bank 1 to bank 5 a to h a to h MC14489 #1 MC14489 #2 MC14489 #5 data in clock enable data out data in clock enable data out data in clock enable data out optional c0 c1 c2 c3 c4 c5 c6 c7 cmos mcu/mpu don't care 1st byte shifted in 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte don't care don't care don't care configuration register of device #3 configuration register of device #5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 1st byte shifted in 2nd byte 4th byte 5th byte 6th byte 14th byte 15th (last) byte display register of device #5 display register of device #4 display register of device #1 bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble (a) cascading five devices note: enable (which initially must be inactive high) is kept activelow during the entire 13byte configuration transfer or 15byte display transfer . when enable is brought back high, either a 13 or 15byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer . bank 1 to bank 5 a to h MC14489 #3 data in clock enable data out 9th byte 10th byte 11th byte 13th (last) byte don't care don't care configuration register of device #1 configuration register of device #2 13th byte h bits and dimmer bit bank 5 nibble don't care 3rd byte configuration register of device #4 12th byte don't care bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble h bits and dimmer bit bank 5 nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble h bits and dimmer bit bank 5 nibble (b) configuration registers (c) display registers
MC14489 motorola 15 figure 15. commoncathode led display with dialadjusted brightness v ss cmos mcu/mpu rx led display MC14489 8 5 + 5 v r1 r2 v dd + 5 v note: r1 limits the maximum current to avoid damaging the display and/or the MC14489 due to overheating. see the thermal considerations section. an 1/8 watt resistor may be used for r1. r2 is a 1 k w or 5 k w potentiometer ( 1/8 watt). r2 may be a lightsensitive resistor. figure 16. driving 5 1/2 digits 4 universal overflow (a1o or ahalfdigito) MC14489 5 h 3 a to g 3 2 1 bank outputs 7 use to drive lamp or minus sign 5digit display input lines note: a universal overflow pins out all anodes and cathodes.
MC14489 motorola 16 figure 17. 25lamp application 3 bank 5 bank 4 bank 3 bank 2 bank 1 d a b c e f g h cmos mcu/mpu nc nc nc MC14489 these lamps dependently controlled with bits d20, d21, and d22* these lamps independently controlled with bits d0 to d19 * if required, this group of lamps can be independently controlled. t o accomplish independent control, only connect lamps to bank 1 and bank 2 for output h (two lamps). then, use bits d20, d21, and d22 for control of these two lamps.
MC14489 motorola 17 figure 18. 4digit display plus decimals with four annunciators or 41/2digit display plus sign 4 cmos mcu/mpu a to d bank 1 to bank 4 bank 5 MC14489 4 4 e to h 3 4 ? figure 19. compact display system with three components input lines 3 8 14 MC14489 muxed 5digit monolithic display (cluster) hewlettpackard 50827415 or equivalent 12 3 6 2 10 8 5 1 13 4 9 7 6 5 4 2 1 20 19 17 16 15 13 9 7
MC14489 motorola 18 thermal considerations the MC14489 is designed to operate with a chipjunction temperature (t j ) ranging from 40 to 130 c, as indicated in the electrical characteristics tables. the ambient operating temperature range (t a ) is dependent on r q ja , the internal chip current, how many anode drivers are used, the number of bank drivers used, the drive current, and how the package is cooled. the maximum ratings table gives the thermal re - sistance, junctiontoambient, of the MC14489 mounted on a pc board using natural convection to be 90 c per watt for the plastic dip . the sog thermal resistance is 100 c per watt. the following general equation (1) is used to determine the power dissipated by the MC14489. p t = p d + p i (1) where p t = total power dissipation of the MC14489 p d = power dissipated in the driver circuitry (mw) p i = power dissipated by the internal chip circuitry (mw) the equations for the two terms of the general equation are: p d = (i oh ) (n)(v dd v led )(b/5) (2) (3) p i = (1.5 ma)(v dd ) + i rx (v dd i rx rx) where i oh = peak anode driver current (ma) i rx = i oh /10, with i oh = the peak anode driver current (ma) when the dimmer bit is high n = number of anode drivers used b = number of bank drivers used rx = external resistor value (k w ) v dd = maximum supply voltage, referenced to v ss (volts) v led = minimum anticipated voltage drop across the led 1.5 ma = operating supply current of the MC14489 the f ollowing t w o e xample s s ho w h o w t o c alculat e t he maximum allowable ambient temperature. worstcase analysis example 1: 5digit display with decimals (5 banks and 8 anode drivers) dip without heat sink on pc board i oh = 20 ma max v led = 1.8 v min v dd = 5.25 max p d = (20)(8)(5.25 1.8)(5/5) = 552 mw ref. (2) p i = (1.5)(5.25) + 2[5.25 2(2)] = 10 mw ref. (3) therefore, p t = 552 + 10 = 562 mw ref. (1) and d t chip = r q ja p t = (90 c/w)(0.562) = 51 c finally, the maximum allowable t a = t j max d t chip = 130 51 = 79 c that is, if t a = 79 c, the maximum junction temperature is 130 c. the chip' s average temperature for this example is lower than 130 c because all segments are usually not illu - minated simultaneously for an indefinite period. worstcase analysis example 2: 16 lamps (4 banks and 4 anode drivers) sog without heat sink on pc board i oh = 30 ma max v led = 1.8 v min v dd = 5.5 max p d = (30)(4)(5.5 1.8)(4/5) = 355 mw ref. (2) p i = (1.5)(5.5) + 3[5.5 3(1.0)] = 16 mw ref. (3) therefore, p t = 355 + 16 = 371 mw ref. (1) and d t chip = r q ja p t = (100 c/w)(0.371) = 37 c finally, the maximum allowable t a = t j max d t chip = 130 37 = 93 c to extend the allowable ambient temperature range or to reduce t j , w hic h e xtends c hi p l ife , a h ea t s in k s uc h a s shown in figure 20 can be used in highcurrent applications. alternatively, heatspreader techniques can be used on the pc board, such as running a wide trace under the MC14489 and u sin g t herma l p aste . w ide , r adia l t race s f rom t he MC14489 leads also act as heat spreaders. aavid #5804 or equivalent (tel. 603/5244443, fax 603/5281478) motorola cannot recommend one supplier over another and in no way suggests that this is the only heat sink supplier . figure 20. heat sink
MC14489 motorola 19 table 2. led lamp and commoncathode display manufacturers supplier contact information qt optoelectronics phone: (800) 5336786 fax: (214) 4470784 hewlettpackard (hp), components group contact your local hp components sales office industrial electronic engineers (iee), component products div. phone: (818) 7870311 fax: (818) 9019046 purdy electronics corp., and product line phone: (408) 5238210 fax: (408) 7331287 note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of led suppliers. package dimensions p suffix plastic dip case 73803 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e g f d 20 pl j 20 pl l m -t- seating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b
MC14489 motorola 20 dw suffix sog package case 751d04 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 MC14489/d ?

▲Up To Search▲

Price & Availability of MC14489

	To Download MC14489 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .